For many years, gate arrays have been used to provide quick-turnaround (quick-turn), low non-recurring-expense (NRE) semiconductor devices for a variety of purposes. Traditionally, wafers are processed up to but not including the first (bottom) metal layer, and saved in inventory. When a customer orders a device to be fabricated for a specific application (an application specific integrated circuit or xe2x80x9cASICxe2x80x9d), the customer only pays for the masks to configure the metal layers, and not the transistor layers below. Thus, NRE is reduced. The wafers can be completed quickly, since only the metal layers remain to be fabricated, reducing turn-around time.
In some of the above-described devices, general purpose, random access memory (RAM) is needed. At one time, to satisfy this need, a separate area of RAM was simply incorporated into the chip. FIG. 1 illustrates such a device. In FIG. 1, blocks of RAM, 100, are incorporated onto chip 102, together with the gate array logic transistors, 104. Metal layers. 105 are provided on top of the chip for routing the gate array logic, and the chip is provided with connection pads 106.
Recently more and more layers of metal have been incorporated into gate array semiconductor devices. Rather than two or three layers of metal, six to eight layers of metal is now common. As a result, gate arrays are no longer very low-NRE, or quick-turn. In order to regain the advantages of earlier gate arrays, several vendors have developed logic arrays, consisting of multiple, substantially identical logic cells, which can be configured for an application with either fewer or cheaper masks. In the case of fewer masks, the total number of metal layers and hence masks used to create the finished device often does not change. Rather, only a reduced subset of the total number of metal layers in a finished device is used to impart the custom configuration to the device. For example, so-called xe2x80x9cone-maskxe2x80x9d devices, in which only a single metal layer and hence a single mask imparts customization, can reduce both NRE and turn-time. A side-effect of such techniques is that more area is required in order to complete routing. This naturally leads to a mismatch in the metal area required for routing and the transistor area required to implement logicxe2x80x94extra, unused semiconductor is left in the device. The logic cells in the device are referred to as being xe2x80x9cmetal-limited.xe2x80x9d
FIG. 2 illustrates the semiconductor layer of a metal-limited device 200. The device consists of an array of identical cells, as shown at 202. In each cell only a portion of the semiconductor, for example the portion shown at 204, is used.
Various ideas have been proposed to make use of the extra silicon in the cells of these metal-limited devices. For example, the extra semiconductor can be used to provide field programmable gate array (FPGA) functionality, test circuitry or to increase device density. Devices are also available that use the extra space to incorporate random access memory (RAM) into each cell. The RAM can then be used to program look-up-tables (LUT""s) in the cells. If a particular cell""s logic is to be unused, the RAM in that cell can be used as a stand-alone, general purpose RAM device, which can alleviate the need to add a block of RAM to the chip as shown in FIG. 1. However, the RAM in the cell of such a device cannot be used simultaneously with the gate array logic in the cell.
The present invention provides for the incorporation of RAM into the logic array in a distributed fashion, so that a single cell fabric can provide both logic and RAM functionality simultaneously while substantially maximizing the amount of configurable metal for routing. The extra semiconductor area in the cells of a metal limited device is used to implement general purpose RAM that never needs to be used to configure the logic. Common select lines and read/write lines for the RAM are embedded in the base cells so that the configurable metal (whether via or actual metal layer) over the RAM can be used for routing logic.
According to at least some embodiments of the invention, a mask-configurable semiconductor chip is built to be finished by providing masks to be used in routing metal layers on top of the chip. The chip has an array of logic cells, and at least some logic cells in the array comprise both mask-configurable gate array logic, and random access memory (RAM). The RAM in each of those cells is connected to common select and read/write lines to form distributed RAM so that the RAM is usable simultaneously with the mask-configurable gate array logic.
In some embodiments, the chip is designed to be configured (customized) using less than the actual number of metal (including via) layer masks that will actually be used to create a final device. In some cases, this configuration will be accomplished with a single metal layer mask, which may be either a mask designed to create a layer of actual metal traces, or a layer of vias which move signals between metal layers.
In any case, a completed device is made by first forming the semiconductor layer where cells contain both mask-configurable gate array logic and random access memory (RAM) as described above. Then, the plurality of metal layers are formed top of the semiconductor layer for routing connections. At least some of the plurality of metal layers are customized and are used to configure the device for a specific application.